The present invention relates to a capacitive load element, and more particularly to a capacitive load element of a signal delay circuit.
A digital control clock delay circuit may be classified into an analog delay circuit and a digital delay circuit based on the architecture and adjustment mechanism.
The analog delay circuit is characterized by using the analog control signal, and generally includes a digital to analog circuit and a delay circuit. An external digital control signal is converted into an analog voltage through a digital to analog converter (DAC). The delay circuit consists of a differential pair circuit consisting of N-type or P-type transistors and different load resistors or load capacitors. Parameters, such as bias current, and load capacitance or load resistance at the output end, of the delay elements are finely adjusted to change the signal delay time. Although achieving a high resolution and high anti-noise capability, the analog delay circuit has a complicated design and a high cost. In the design of the analog delay circuit, a plurality of iterative fine adjustments of the sizes and operating points of the elements must be performed, and the circuit needs to be redesigned whenever the process is updated. The digital delay circuit directly controls the delay unit through the digital control signal, and the delay unit consists of an inverter, a transmission gate, a multiplexer, an NAND gate, an NOR gate, etc.
FIG. 1 shows a digital delay circuit in the prior art. The digital delay circuit consists of a transmission gate 10, a first inverter 11, and a second inverter 12. Referring to FIG. 1, the first inverter 11 receives a signal at an input end In, and outputs the signal through an output end Out after inverting the signal. An input end and an output end of the transmission gate 10 are directly interconnected, and then connected to the output end Out of the first inverter 11. A control end of the transmission gate 10 is controlled by a control signal Ctrl. The second inverter 12 receives the control signal Ctrl, and outputs an inverted control signal Ctrlb to another control end of the transmission gate 10.
FIG. 2 shows an equivalent circuit diagram of the transmission gate 10 in FIG. 1. The equivalent circuit consists of a PMOS transistor 13 and an NMOS transistor 14. A source and a drain of the PMOS transistor 13 are interconnected, and then connected to the output end Out of the first inverter 11. A gate of the PMOS transistor 13 receives the inverted control signal Ctrlb. Likewise, a source and a drain of the NMOS transistor 14 are also interconnected, and then connected to the output end of the first inverter 11. A gate of the NMOS transistor 14 receives the control signal Ctrl. In the figure, CN represents the capacitance of the NMOS transistor 14 at the output end, and CP represents the capacitance of the PMOS transistor 13 at the output end.
When the control signal Ctrl received by the control end of the transmission gate 10 is logic 0, no matter the logic level at the output end of the first inverter 11 is 1 or 0, the capacitance of the transmission gate 10 is equal to the sum of the capacitance of the NMOS transistor when turned off and the capacitance of the PMOS transistor when turned off.
When the control signal Ctrl received by the control end of the transmission gate 10 is logic 1, and the logic level at the output end of the first inverter 11 is 0, the capacitance at the output end of the first inverter 11 is equal to the sum of the capacitance of the NMOS transistor when turned on and the capacitance of the PMOS transistor when turned off When the logic level at the output end of the first inverter 11 is 1, the capacitance at the output end of the first inverter 11 is equal to the sum of the capacitance of the NMOS transistor when turned off and the capacitance of the PMOS transistor when turned on. FIGS. 3A and 3B are schematic views showing parasitic capacitance changes at the output end of the first inverter 11 under different control signals. FIG. 3A is a schematic view showing the capacitance changes of the PMOS transistor indicated by a curve 15 and the capacitance changes of the NMOS transistor indicated by a curve 16 when the control signal Ctrl is logic 0. FIG. 3B is a schematic view showing the capacitance changes of the PMOS transistor indicated by a curve 17 and the capacitance changes of the NMOS transistor indicated by a curve 18 when the control signal Ctrl is logic 1. As shown in the figure, the transmission delay of the circuit is increased with the increase of the parasitic capacitance due to the change of the control signal.
FIG. 4 is a schematic view of another delay circuit in the prior art. The delay circuit consists of an inverter 20 and an NAND gate 21. The inverter 20 receives a signal at an input end In, and outputs the signal through an output end Out after inverting the signal. The NAND gate 21 has a first input end, a second input end, and an output end. The first input end of the NAND gate 21 is electrically connected to the output end Out of the inverter 20, the second input end of the NAND gate 21 receives a control signal Ctrl, and the output end of the NAND gate 21 is floating.
FIG. 5 is an equivalent circuit diagram of the NAND gate 21 in FIG. 4. The equivalent circuit consists of PMOS transistors 22, 24 and NMOS transistors 23, 25. FIGS. 6A and 6B are schematic views showing parasitic capacitance changes at the output end Out of the inverter 20 under different control signals.
In FIG. 6A, when the control signal Ctrl is logic 0, a curve 26 indicates parasitic capacitance changes at the output end of the inverter 20 generated by the PMOS transistor 22, and a curve 27 indicates parasitic capacitance changes at the output end of the inverter 20 generated by the NMOS transistor 23. In FIG. 6B, when the control signal Ctrl is logic 1, a curve 28 indicates parasitic capacitance changes at the output end of the inverter 20 generated by the PMOS transistor 22, and a curve 29 indicates parasitic capacitance changes at the output end of the inverter 20 generated by the NMOS transistor 23.
When the control signal Ctrl is logic 0, no matter the logic level at the output end of the inverter 20 is 1 or 0, the NMOS transistor 23 is turned off The PMOS transistor 22 is turned on when the logic level at the output end of the inverter 20 is 0, and is turned off when the output level is 1. When the control signal Ctrl is logic 1, the capacitance of the NMOS transistor 23 changes with the output voltage, wherein the NMOS transistor 23 is turned on when the output level is 1, and turned off when the output level is 0. Likewise, the capacitance of the PMOS transistor 22 changes with the output voltage, which is almost the same as the circumstance when the control signal Ctrl is logic 0, but has the following difference. When the output voltage is neither logic 0 nor 1, the NMOS transistor 23 is temporarily turned on. Thus, the turn-on range of the PMOS transistor 22 is slightly expanded, and the capacitance changes are slightly increased. Compared with the capacitance changes of the NMOS transistor 23, the capacitance changes of the PMOS transistor 22 are negligible, and thereby a capacitance difference of the NMOS transistor 23 between the turn-on and turn-off can be generated through the control signal Ctrl. Referring to FIGS. 6A and 6B, due to the capacitance changes, the transmission delay of the circuit is increased. Further, after comparison between FIGS. 6B and 3B, the signal delay circuit in FIG. 4 has slight capacitance changes than that in FIG. 1, thus generating subtle clock delay.